A charge transfer device such as a CCD imager includes a charge transfer section for transporting electric charge from an array of light sensitive pixel sites to an output circuit structure. The output structure employs a resettable floating diffusion that is used for charge to voltage conversion. This conversion generates an output signal that is typically processed with a sampling technique to measure the amplitude of the signal from each pixel site. For instance, correlated double sampling is commonly used in order to obtain low noise performance. Correlated double sampling is equivalent to subtracting a reset reference level from an image level for each output pixel from the CCD imager.
A CCD output circuit 2 and a subsequent sampling circuit 4, both known in the prior art, are shown in FIG. 1. The output circuit 2 converts a photoelectrically generated signal charge from a CCD imager 6 to an output voltage signal. The output circuit 2 is, for example, a floating diffusion amplifier structure formed on a common substrate with the imager 6. The sampling circuit 4 extracts the image information from the output signal. Charge packets from a photosensitive area comprising an array of imager photosites 8 are transferred through a transfer gate 9 into a horizontal output register 10. These charge packets are shifted horizontally to a floating diffusion output 12 via output gate 13 by horizontal transport clocks TRANSPORT-1 and TRANSPORT-2, each having waveforms with a pattern of transitions that cause shifting of the image charge. The potential of the floating diffusion 12, which changes linearly in proportion to the number of electrons in the charge packet, is applied to the input gate of a two stage source follower circuit 14, producing an output signal at V.sub.out. A reset transistor 16 driven by a reset clock (RESET) recharges the floating diffusion 12 to the positive potential V.sub.rd before the arrival of each new charge packet from the horizontal output register 10.
FIG. 2 shows signal waveforms active in the circuits shown in FIG. 1, including the signal waveform V.sub.out at the output of the source follower 14. This waveform contains three components: the reset clock feedthrough (V.sub.ft), the reset reference level (V.sub.reset), and the image level (V.sub.image). The reset and image levels can each be characterized as pedestals (reset pedestal and image pedestal) covering defined temporal regions within the waveform. The feed through V.sub.ft occurs as a result of capacitive coupling between the reset transistor 16 and the floating diffusion 12. When the floating diffusion 12 is reset, the exact reset voltage is affected by "thermal" noise, whose level depends on the capacitance of the floating diffusion 12 and the temperature. The same random reset noise voltage affects the level of both the reset level pedestal V.sub.reset and the image level pedestal V.sub.image.
By taking the difference between samples of the pedestal levels of V.sub.reset and V.sub.image for each pixel, this "thermal" noise can be eliminated. This also reduces low frequency noise from the two stage source follower output amplifier 14. The signal V.sub.out from the source follower circuit 14 is applied to a clamp circuit 18, which clamps the reset level pedestal V.sub.reset. The output of the clamp 18 and the signal V.sub.out are simultaneously applied to the sample/hold circuits 20 and 22, which respectively sample the reset level pedestal V.sub.reset (thus effecting a delay in the reset level pedestal) and the image level pedestal V.sub.image. FIG. 2 shows the sampling waveforms CLAMP and SAMPLE that respectively drive the clamp circuit 18 and the sample/hold circuits 20 and 22. A noise-free difference signal, which is the image signal shown in FIG. 2, is taken between the outputs of the sample/hold circuits 20 and 22 by a subtracting circuit 24. A clock generator 26 provides the signals CLAMP and SAMPLE, as well as the transport clocks TRANSPORT-1 and TRANSPORT-2, and the reset clock RESET.
Pixel summing is based on reading out the charge data at 1/2 resolution of the CCD imager in 1/2 of the time. This is accomplished by adding charge together from two or more adjacent pixels at the output structure 2 of the imager 6. A known timing technique for pixel summing from two adjacent pixels, as shown in FIG. 3, involves doubling the clock rate of the symmetrical complimentary transport clocks TRANSPORT-1 and TRANSPORT-2 in relation to the clock RESET that resets the floating diffusion. One of the results of such doubling is that the output signal V.sub.out changes in profile reducing the pedestal length of both the reset level pedestal and the image level pedestal (compare the pedestals in FIG. 3 with those in FIG. 2). This change in profile may require changes in other system signal processing clocks such as the correlated double sampling clocks CLAMP and SAMPLE (see FIG. 2) to compensate for the narrower pedestal areas both in terms of pulse width and temporal position. Besides being difficult to accurately align the clamp and sample clocks to the narrower pedestals, the clock change required for such alignment can ultimately ripple through the timing of an entire data path and cause unwanted artifacts in the image signal.